Floating gate memory devices, such as Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) and Flash EPROMs or EEPROMs, are widely used for nonvolatile memories. These devices store charges in a floating gate. The floating gate must hold a charge without refresh for extended periods. The floating gate is charged by hot electron or avalanche injection through a gate oxide between the floating gate and the substrate. Typically, a first layer of polysilicon is used for the floating gate, which is a totally encapsulated and electrically isolated portion of polysilicon. The control gate is formed over the floating gate in a second layer of polysilicon. The floating and control gates are separated by an interpoly dielectric and act as two plates of a capacitor. Transistor source and drain regions are formed below and adjacent to the floating gate.
For a flash cell, the floating gate may be charged by applying a relatively large voltage to the control gate. The voltage on the control gate establishes an electric field in the gate oxide between the floating gate and the substrate. Then a lower voltage pulse is applied between source and drain regions in the substrate. The electric field attracts the electrons generated from the "avalanche" breakdown of the transistor due to the drain and control gate voltages and injects those electrons into the floating gate through the gate oxide. This process of injection charging is referred to as hot electron or avalanche injection.
As the cell spacing of floating gate memory devices is reduced, a very high quality interpoly dielectric is needed to maintain high specific capacitance between the floating gate and the control gate. This dielectric must perform effectively during the application of high charging voltages and also prevent leakage between the floating gate and the control gate after charging. Since information is stored without refresh by charges trapped in the floating gate, it is critical that leakage between the floating gate and the control gate be minimized.
For standard Metal Oxide Silicon (MOS) processes, forming a precision capacitor over a first layer of polysilicon is difficult since the surface of the polysilicon is not as smooth as that of the polished surface of the substrate. The unevenness of the polysilicon can significantly affect the thickness of an oxide insulator formed over the polysilicon. Variations in thickness of an oxide leads to corresponding variations in the specific capacitance between the gates.
U.S. Pat. No. 4,613,956 issued to Patterson et al. on Sep. 23, 1986 presents one solution to the above-referenced problems. Patterson describes an integrated insulating dielectric comprising a composite oxide/nitride or oxide/nitride/oxide dielectric insulator used over the first layer of polysilicon instead of the thermally grown oxide previously used. The composite dielectric disclosed in Patterson has come to be commonly referred to as an "ONO" film stack. The present invention provides an alternative and equally effective interpoly dielectric to the ONO film stack described in Patterson.